Scan driver and organic light-emitting display using same

ABSTRACT

The present invention provides a scanning driver and an organic light-emitting display using the same. The scanning driver comprises a plurality of cascaded structures receiving signals from a first timing clock line (CK1) and a second timing clock line (CK2) with opposite phases, the cascaded structures successively generating output signals (i.e., scanning signals), wherein each of the cascaded structures comprises: a first transistor, connected to a starting signal line or to a scanning output line of a previous cascaded structure; a second transistor, connected to the second timing clock line and to the scanning output line; a third transistor connected to a high-level power supply VGH; a fourth transistor, connected to a low-level power supply VGL and to an output terminal of the third transistor; a fifth transistor, connected to a high-level power supply VGH and to a scanning output line; and a first capacitor, connected between an output terminal of the first transistor and the scanning output line. Arranging a first capacitor C1 between the output terminal of M1 and the scanning output line prevents slight-ON of M2, thus reducing the reverse current at the scanning driver and reducing the power consumption.

TECHNICAL FIELD

The present invention relates to organic light-emitting diode displaysand in particular to a scanning driver capable of reducing powerconsumption and an organic light-emitting display using the scanningdriver.

BACKGROUND

The light-emitting devices used in organic light-emitting displays areorganic light-emitting diodes (OLEDs). Compared with the thin filmtransistors (TFTs) in the existing mainstream flat panel displaytechnology, OLEDs, due to their advantages such as high contrast, wideangle of view, low power consumption, smaller size and the like, areexpected to become prevailing in the next-generation flat panel displaytechnology beyond LCDs, which is one of technologies that are highlyconcerned among the existing flat panel display technology.

A conventional scanning driver circuit is formed by a plurality oftransistors, a starting signal line IN, timing clock lines CLK1 andCLK2, a high-level power supply VGH and a low-level power supply VGL.When the timing clock lines CLK1 and CLK2 hop, due to the presence of aparasitic capacitor in the transistors, a weak reverse current isgenerated in the circuit. Therefore, a reverse current of several ormore milliamperes may be generated when N rows in the entire screen workcollaboratively, thereby leading to non-uniform display on the screenand excessively high power consumption.

SUMMARY Technical Problems

In view of the problem of excessively high power consumption of thescanning driver in the traditional technologies, a device is provided toreduce the reverse current of a scanning driver of an OLED display.

Technical Solution to the Problem

To solve the above technical problem, the present invention provides ascanning driver, including: a plurality of cascaded structures receivingsignals from a first timing clock line and a second timing clock linewith opposite phases, the cascaded structures successively generatingscanning signals. Each of the cascaded structures includes: a firsttransistor connected to a starting signal line or to a scanning outputline of a previous cascaded structure; a second transistor connected tothe second timing clock line and to a scanning output line; a thirdtransistor connected to a high-level power supply VGH, the thirdtransistor including a gate connected to an output terminal of thesecond transistor; a fourth transistor connected to a low-level powersupply VGL and to an output terminal of the third transistor, the fourthtransistor including a gate connected to the first timing clock line; afifth transistor connected to a high-level power supply VGH and to ascanning output line, the fifth transistor including a gate connected toan output terminal of the fourth transistor and to an output terminal ofthe third transistor; and a first capacitor connected between an outputterminal of the first transistor and the scanning output line.

Preferably, each of the cascaded structures further includes a secondcapacitor connected between an output terminal of the first transistorand a fixed potential.

Preferably, the fixed potential is a low-level power supply VGL.

Preferably, the fixed potential is a high-level power supply VGH.

Preferably, a first clock terminal of an odd one of the cascadestructures is connected to the first timing clock line, and a secondclock terminal thereof is connected to the second timing clock line; anda first clock terminal of an even one of the cascade structures isconnected to the second timing clock line, and a second clock terminalthereof is connected to the first timing clock line.

Preferably, the transistors are bidirectional PMOS transistors orbidirectional P-type thin film field effect transistors.

The present invention further provides an organic light-emittingdisplay, including: a pixel array, connected to a data line and ascanning output line; a data driver, configured to provide data signalsto the data line; a scanning driver, configured to provide scanningsignals to the scanning output line; and a timing controller, configuredto provide timing signals and a high-level power supply VGH and alow-level power supply VGL to the scanning driver.

Beneficial Effects of the Invention

The present invention provides the following beneficial effects: Byadding a first capacitor C1 between the output terminal of M1 and thescanning output line, the first capacitor C1 prevents slight-ON of M2when the second timing clock line hops, thus reducing the reversecurrent of the scanning driver, reducing the power consumption, andimproving the quality of display of the screen.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a circuit diagram of an organic light-emitting displayaccording to an embodiment of the present invention;

FIG. 2 is a circuit diagram of a pixel display unit in the organiclight-emitting display;

FIG. 3 is a circuit diagram of a scanning driver according to thepresent invention;

FIG. 4 is a circuit diagram of a cascaded structure 1 of FIG. 3according to a first embodiment;

FIG. 5 is a circuit timing diagram of the cascaded structure 1 of FIG. 4in one frame;

FIG. 6 is a circuit diagram of the cascaded structure 1 of FIG. 3according to a second embodiment; and

FIG. 7 is a circuit diagram of the cascaded structure 1 of FIG. 3according to a third embodiment.

DETAILED DESCRIPTION

FIG. 1 is a circuit diagram an organic light-emitting display accordingto an embodiment of the present invention. As shown in FIG. 1, thisorganic light-emitting display includes a data driver 110 configured toprovide data signals to a data line, a scanning driver 111 configured tosuccessively provide scanning signals to scanning output lines, a timingcontroller 112 configured to provide timing signals and a high-levelpower supply VGH and a low-level power supply VGL to the scanning driver111, and a display unit 113 for a plurality of pixels. The function of ascanning driver circuit is to successively generate scanning signalswhich are to be provided to a display panel to drive pixels in thedisplay panel.

FIG. 2 is a circuit diagram of a pixel display unit in the organiclight-emitting display. As shown in FIG. 2, this pixel circuit includesa transistor T1, a transistor T2 and a capacitor C0. The gate of T1 isconnected to a scanning output line of a scanning driver, and the sourceof T1 is connected to a data line of a data driver. One terminal of thecapacitor C0 is connected to a fixed power supply, and the otherterminal thereof is connected to the drain of T1. The gate of T2 isconnected to the drain of T1, the source thereof is connected to thefixed power supply, and the drain thereof is connected to an OLED.

The working principle of the circuit is as follows: A scanning driverprovides scanning signals to T1 via the scanning output line, and thedata driver provides data signals to T1; and when T1 is turned on, adata voltage is transmitted to the gate of T2, and the TFT T2 generatesa corresponding current which flows to the OLED such that the OLED emitslight.

The scanning driver 111 uses the scanning driver in the followingembodiment.

FIG. 3 is a circuit diagram of a scanning driver according to thepresent invention. As shown in FIG. 3, the scanning driver includes aplurality of cascaded structures, and each of the cascaded structures isconnected to timing clock lines CLK1 and CLK2 with opposite phases, andeach of the cascaded structures successively generates output signals,i.e., scanning signals, to scanning output lines S1 to SN.

Preferably, a first clock terminal of an odd one of the cascadestructures is connected to a first timing clock line, and a second clockthereof is connected to a second timing clock line; and the first clockterminal of an even one of the cascade structures is connected to thesecond timing clock line, and the second clock terminal is connected tothe first timing clock line.

Optionally, a first clock terminal of an odd one of the cascadestructures is connected to a second timing clock line, and a secondclock thereof is connected to a first timing clock line; and the firstclock terminal of an even one of the cascade structures is connected tothe first timing clock line, and the second clock terminal is connectedto the second timing clock line.

FIG. 4 is a circuit diagram of a first embodiment of the cascadedstructure 1 of FIG. 3. As shown in FIG. 4, the cascaded structure 1includes a first transistor M1, a second transistor M2, a thirdtransistor M3, a fourth transistor M4, the fifth transistor M5, a firstcapacitor C1, a starting signal line IN, a first timing clock line CLK1,a second timing clock line CLK2, a high-level power supply VGH and alow-level power supply VGL.

The gate of the first transistor M1 is connected to the first timingclock line CLK1, the source of M1 is connected to the starting signalline IN, and the drain thereof is connected to the gate of the secondtransistor M2. The source of the second transistor M2 is connected tothe second timing clock line CLK2, and the drain thereof is connected tothe scanning output line. The gate of the third transistor M3 isconnected to the drain of the second transistor, the source thereof isconnected to the high-level power supply VGH, and the drain thereof isconnected to the source of the fourth transistor M4. The gate of thefourth transistor M4 is connected to the first timing clock line CLK1,the source thereof is connected to the drain of M3, and the drain of M4is connected to the low-level power supply VGL. The gate of the fifthtransistor M5 is connected to the source of M4, the source of M5 isconnected to the high-level power supply VGH, and the drain of the M5 isconnected to the scanning output line. One terminal of the firstcapacitor C1 is connected to the drain of M1, and the other terminalthereof is connected to the scanning output line.

Preferably, the transistors M1, M2, M3, M4, M5 employ a bidirectionalPMOS transistor or a bidirectional P-type thin film field effecttransistor, and the source and the drain thereof are replaceable.

FIG. 5 is a timing diagram of the cascaded structure of FIG. 4 in oneframe. As shown in FIG. 5, IN is a timing diagram of a starting signalline, CLK1 is a timing diagram of a first timing clock line, CLK2 is atiming diagram of a second timing clock line, N1 is a timing diagram ofan output terminal of M1, and S1 to SN respectively are timing diagramsof scanning output lines of cascaded structures 1 to n. The workingprinciple of the circuit of the cascaded structure 1 is as follows.

When a signal of the starting signal line IN hops to a low level, CLK1hops to a low level, and CLK2 hops to a high level, M1 is turned on andan output voltage N1 thereof is low-level VGL+Vth (Vth is the absolutevalue of the threshold voltage). The capacitor C1 is charged. The gateof M2 is in a low level and the source thereof is in a high level, M2 isthus turned on such that S1 outputs a high level. Since CLK1 is in a lowlevel and M4 is also turned on and outputs a low level to the gate ofM5, M5 is turned on such that M5 outputs a high level VGH to S1.

When the signal of the starting signal line IN hops to a high level,CLK1 hops to a high level, and CLK2 hops to a low level, M1 is turnedoff. When CLK2 is in a high level, due to the discharging of thecapacitor C1, N1 may be temporarily maintained in a low level VGL+Vth(Vth is the absolute value of the threshold voltage), and M2 ismaintained in an ON state; and When CLK2 becomes from a high level to alow level, due to the coupling of the capacitor C1, the voltage ofterminal N1 drops from VGL+Vth to 2 VGL+Vth (Vth is the absolute valueof the threshold voltage of M1), and M2 is still maintained in an ONstate, such that the drain of M2 outputs a low level to S1. The gate ofM3 is in a low level and the source thereof is in a high level, suchthat M3 is turned on and outputs a high level. As a result, the gate ofM5 is in a high level, such that M5 is turned off. Thus, S1 may bemaintained to output a stable low level.

When the starting signal line IN is continuously maintained in a highlevel while CLK1 is in a low level and CLK2 is in a high level, M1 isturned ON, terminal N1 is turned to a high level, C1 is charged again.The gate of M2 is turned to a high level, such that M2 is turned off. M4is turned on since CLK1 is turned to a low level, and outputs a lowlevel to the gate of M5. M5 is turned on, and outputs a high level VGHto S1. When CLK1 is in a high level and CLK2 is in a low level, M1 isturned off, and terminal N1 is maintained in a high level such that M2is also turned off. Furthermore, slight-ON of M2 is prevented due to thedischarging of C1. CLK1 is in a high level, and M4 is turned off. Thedrain of M4 is maintained in a low level, such that M5 is continuouslymaintained in an ON state and S1 continuously outputs a high level.

In a similar manner, when the starting signal line IN is maintained in ahigh level in one frame, S1 continuously outputs a high level.

In the absence of the capacitor C1, after CLK1 is turned to a highlevel, M1 is turned off, and the voltage of terminal N1 drops quickly.Due to the presence of a parasitic capacitor in M2, M2 is slightlyturned on in a process during which CLK2 is turned from a high level toa low level. Since M5 has been turned on, a reverse current flowing fromVGH to terminal OUT and then from terminal OUT to CLK2 is generated.When the plurality of cascaded structures work at the same time, areverse current of several or higher milliamperes will be generated, lowpotential of CLK2 and CLK 1 will rise. As a result, the powerconsumption of the driving scanner is excessively high and the displayof the screen becomes non-uniform, and consequently the quality ofdisplay of the screen is significantly influenced.

In the presence of the capacitor C1, after M1 is turned off, thecapacitor C1 can maintain the original high level of the terminal N1,thereby preventing the slight-ON of M2, reducing the power consumptionof the scanning driver, and improving the quality of display of thescreen.

Preferably, the transistors are bidirectional PMOS transistors orbidirectional P-type thin film field effect transistors.

Similarly, the cascaded structures 2 to n successively receive signalsfrom a scanning output line of a previous cascaded structure, and thetiming hopping thereof is as shown in FIG. 5.

In the technical solution according to this embodiment, by adding afirst capacitor C1 between the output terminal of M1 and the scanningoutput line, the first capacitor C1 prevents slight-ON of M2 when thesecond timing clock line hops, thus reducing the reverse current of thescanning driver, reducing the power consumption, and improving thequality of display of the screen.

FIG. 6 is a circuit diagram of the cascaded structure 1 of FIG. 3according to a second embodiment. The circuit further includes a secondcapacitor C2 connected between the output terminal of the firsttransistor M1 and the fixed potential.

The fixed potential is a low-level power supply VGL.

In the technical solution according to this embodiment, the secondtransistor C2 can further maintain the voltage of terminal N1 stable andminimize the voltage difference of the first capacitor C1 and thecurrent leakage.

FIG. 7 is a circuit diagram of the cascaded structure 1 of FIG. 3according to a third embodiment. The circuit further includes a secondcapacitor C2 connected between the output terminal of the firsttransistor M1 and the fixed potential.

The fixed potential is a high-level power supply VGH.

In the technical solution according to this embodiment, the secondtransistor C2 can further maintain the voltage of terminal N1 stable andminimize the voltage difference of the first capacitor C1 and thecurrent leakage.

In another embodiment illustrating the organic light-emitting displayaccording to the present invention, the organic light-emitting displayincludes a data driver configured to provide data signals to a dataline, a scanning driver configured to successively provide scanningsignals to scanning output lines, a timing controller configured toprovide timing signals and a high-level power supply VGH and a low-levelpower supply VGL to the scanning driver, and a display unit for aplurality of pixels. The function of a scanning driver circuit is tosuccessively generate scanning signals provided to a display panel todrive pixels in the display panel.

The scanning driver includes a plurality of cascaded structures, andeach of the cascaded structures is connected to timing clock lines CLK1and CLK2 with opposite phases, and each of the cascaded structuressuccessively generates output signals, i.e., scanning signals, toscanning output lines S1 to SN.

Each of the cascaded structures specifically includes a first transistorM1, a second transistor M2, a third transistor M3, a fourth transistorM4, a fifth transistor M5, a first capacitor C1, a starting signal lineIN, a first timing clock line CLK1, a second timing clock line CLK2, ahigh-level power supply VGH and a low-level power supply VGL.

Preferably, a first clock terminal of an odd one of the cascadestructures is connected to a first timing clock line, and a second clockthereof is connected to a second timing clock line; and the first clockterminal of an even one of the cascade structures is connected to thesecond timing clock line, and the second clock terminal is connected tothe first timing clock line.

Preferably, the transistors are bidirectional PMOS transistors orbidirectional P-type thin film field effect transistors.

The specific circuit structures are the same as the above embodiment andwill not be repeated here.

In the technical solution according to this embodiment, by adding afirst capacitor C1 between the output terminal of M1 and the scanningoutput line, the first capacitor C1 prevents slight-ON of M2 when thesecond timing clock line hops, thus reducing the reverse current of thescanning driver, reducing the power consumption, and improving thequality of display of the screen.

In another embodiment illustrating the organic light-emitting displayaccording to the present invention, the organic light-emitting displayincludes a data driver configured to provide data signals to a dataline, a scanning driver configured to successively provide scanningsignals to scanning output lines, a timing controller configured toprovide timing signals and a high-level power supply VGH and a low-levelpower supply VGL to the scanning driver, and a display unit for aplurality of pixels. The function of a scanning driver circuit is tosuccessively generate scanning signals provided to a display panel todrive pixels in the display panel.

The scanning driver includes a plurality of cascaded structures, andeach of the cascaded structures is connected to timing clock lines CLK1and CLK2 with opposite phases, and each of the cascaded structuressuccessively generates output signals, i.e., scanning signals, toscanning output lines S1 to SN.

Each of the cascaded structures specifically includes a first transistorM1, a second transistor M2, a third transistor M3, a fourth transistorM4, a fifth transistor M5, a first capacitor C1, a starting signal lineIN, a first timing clock line CLK1, a second timing clock line CLK2, ahigh-level power supply VGH and a low-level power supply VGL. Thecircuit further includes a second transistor C2 connected between theoutput terminal of the first transistor M1 and the fixed potential. Thefixed potential is a low-level power supply VGL.

The specific circuit structures are the same as the above embodiment andwill not be repeated here.

In the technical solution according to this embodiment, the secondtransistor C2 can further maintain the voltage of terminal N1 stable andminimize the voltage difference of the first capacitor C1 and thecurrent leakage.

In another embodiment illustrating the organic light-emitting displayaccording to the present invention, the organic light-emitting displayincludes a data driver configured to provide data signals to a dataline, a scanning driver configured to successively provide scanningsignals to scanning output lines, a timing controller configured toprovide timing signals and a high-level power supply VGH and a low-levelpower supply VGL to the scanning driver, and a display unit for aplurality of pixels. The function of a scanning driver circuit is tosuccessively generate scanning signals provided to a display panel todrive pixels in the display panel.

The scanning driver includes a plurality of cascaded structures, andeach of the cascaded structures is connected to timing clock lines CLK1and CLK2 with opposite phases, and each of the cascaded structuressuccessively generates output signals, i.e., scanning signals, toscanning output lines S1 to SN.

Each of the cascaded structures specifically includes a first transistorM1, a second transistor M2, a third transistor M3, a fourth transistorM4, a fifth transistor M5, a first capacitor C1, a starting signal lineIN, a first timing clock line CLK1, a second timing clock line CLK2, ahigh-level power supply VGH and a low-level power supply VGL. Thecircuit further includes a second transistor C2 connected between theoutput terminal of the first transistor M1 and the fixed potential. Thefixed potential is a high-level power supply VGH.

The specific circuit structures are the same as the above embodiments,which are thus not described herein any further.

In the technical solution according to this embodiment, the secondtransistor C2 can further maintain the voltage of terminal N1 stable andminimize the voltage difference of the first capacitor C1 and thecurrent leakage.

It should be noted that, the above embodiments are merely provided forexplaining but not limiting the present invention, and the presentinvention is not limited to the examples list above. Any technicalsolutions and improvements made without departing from the spirit andscope of the resent invention should be included in the scope defined bythe claims of the present invention.

What is claimed is:
 1. A scanning driver, comprising: a plurality ofcascaded structures receiving signals from a first timing clock line anda second timing clock line with opposite phases, the cascaded structuressuccessively generating scanning signals, wherein each of the cascadedstructures comprises: a scanning output line, used to output thescanning signals; a first transistor, connected to a starting signalline or to a the scanning output line of the previous cascadedstructure, the first transistor comprising a gate connected to the firsttiming clock line; a second transistor, connected to the second timingclock line and the scanning output line, the second transistorcomprising a gate connected to an output terminal of the firsttransistor; a third transistor, connected to a high-level power supplyVGH, the third transistor comprising a gate connected to an outputterminal of the second transistor; a fourth transistor, connected to alow-level power supply VGL and to an output terminal of the thirdtransistor, the fourth transistor comprising a gate connected to thefirst timing clock line; a fifth transistor, connected to a high-levelpower supply VGH and to a the scanning output line, the fifth transistorcomprising a gate connected to an output terminal of the fourthtransistor and to an the output terminal of the third transistor; and afirst capacitor, connected between an the output terminal of the firsttransistor and the scanning output line.
 2. The scanning driveraccording to the claim 1, wherein each of the cascaded structuresfurther comprises: a second capacitor, connected between the outputterminal of an the first transistor and a fixed potential.
 3. Thescanning driver according to the claim 2, characterized in that thefixed potential is a the low-level power supply VGL.
 4. The scanningdriver according to claim 3, wherein the transistors first through fifthtransistor are bidirectional PMOS transistors or bidirectional P-typethin film field effect transistors.
 5. An organic light-emittingdisplay, comprising a pixel array, connected to a data line and a thescanning output line; a data driver, configured to provide data signalsto the data line; athe scanning driver of claim 4, configured to providescanning signals to the scanning output lineas defined in claim 4; and atiming controller, configured to provide timing signals and a thehigh-level power supply VGH and a the low-level power supply VGL to thescanning driver.
 6. An organic light-emitting display, comprising apixel array, connected to a data line and a the scanning output line; adata driver, configured to provide data signals to the data line; athescanning driverdrive of claim 3, configured to provide scanning signalsto the scanning output lineas defined in claim 3; and a timingcontroller, configured to provide timing signals and a the high-levelpower supply VGH and a the low-level power supply VGL to the scanningdriver.
 7. The scanning driver according to the claim 2, wherein thefixed potential is a the high-level power supply VGH.
 8. The scanningdriver according to claim 7, wherein the transistors first through fifthtransistor are bidirectional PMOS transistors or bidirectional P-typethin film field effect transistors.
 9. An organic light-emittingdisplay, comprising a pixel array, connected to a data line and a thescanning output line; a data driver, configured to provide data signalsto the data line; athe scanning driverdrive of claim 8, configured toprovide scanning signals to the scanning output lineas defined in claim8; and a timing controller, configured to provide timing signals and athe high-level power supply VGH and a the low-level power supply VGL tothe scanning driver.
 10. An organic light-emitting display, comprising apixel array, connected to a data line and a the scanning output line; adata driver, configured to provide data signals to the data line; athescanning driverdrive of claim 7, configured to provide scanning signalsto the scanning output lineas defined in claim 7; and a timingcontroller, configured to provide timing signals and a the high-levelpower supply VGH and a the low-level power supply VGL to the scanningdriver.
 11. The scanning driver according to claim 2, wherein thetransistors first through fifth transistor are bidirectional PMOStransistors or bidirectional P-type thin film field effect transistors.12. An organic light-emitting display, comprising a pixel array,connected to a data line and a the scanning output line; a data driver,configured to provide data signals to the data line; athe scanningdriver of claim 11, configured to provide scanning signals to thescanning output lineas defined in claim 11; and a timing controller,configured to provide timing signals and a the high-level power supplyVGH and a the low-level power supply VGL to the scanning driver.
 13. Anorganic light-emitting display, comprising a pixel array, connected to adata line and a the scanning output line; a data driver, configured toprovide data signals to the data line; athe scanning driver of claim 2,configured to provide scanning signals to the scanning output lineasdefined in claim 2; and a timing controller, configured to providetiming signals and a the high-level power supply VGH and a the low-levelpower supply VGL to the scanning driver.
 14. The scanning driveraccording to the claim 1, wherein a first clock terminal of an odd oneof the cascade structures is connected to the first timing clock line,and a second clock terminal thereof is connected to the second timingclock line; and a first clock terminal of an even one of the cascadestructures is connected to the second timing clock line, and a secondclock terminal thereof is connected to the first timing clock line. 15.The scanning driver according to claim 14, wherein the transistors firstthrough fifth transistor are bidirectional PMOS transistors orbidirectional P-type thin film field effect transistors.
 16. An organiclight-emitting display, comprising a pixel array, connected to a dataline and a the scanning output line; a data driver, configured toprovide data signals to the data line; athe scanning driver of claim 15,configured to provide scanning signals to the scanning output line asdefined in claim 15; and a timing controller, configured to providetiming signals and a the high-level power supply VGH and a the low-levelpower supply VGL to the scanning driver.
 17. An organic light-emittingdisplay, comprising a pixel array, connected to a data line and a thescanning output line; a data driver, configured to provide data signalsto the data line; athe scanning driver of claim 14, configured toprovide scanning signals to the scanning output lineas defined in claim14; and a timing controller, configured to provide timing signals and athe high-level power supply VGH and a the low-level power supply VGL tothe scanning driver.
 18. The scanning driver according to claim 1,wherein the transistors first through fifth transistor are bidirectionalPMOS transistors or bidirectional P-type thin film field effecttransistors.
 19. The scanning driver according to claim 18, wherein thetransistors are bidirectional PMOS transistors or bidirectional P-typethin film field effect transistors.
 20. An organic light-emittingdisplay, comprising a pixel array, connected to a data line and a thescanning output line; a data driver, configured to provide data signalsto the data line; athe scanning driver of claim 1, configured to providescanning signals to the scanning output lineas defined in claim 1; and atiming controller, configured to provide timing signals and a thehigh-level power supply VGH and a the low-level power supply VGL to thescanning driver.